1. Field of the Disclosure
Serial scan and Scan-BIST (Built In Self Test) architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon the previously described low power Scan and Scan-BIST methods. These previously described methods use split scan paths to reduce power consumption. The disclosed improvement provides for the referenced low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures. A delay test captures a response from the logic circuit a clock time after application of a stimulus.
2. Description of Related Art
In FIG. 1, a circuit 100 includes a conventional scan architecture configured for a test. In the normal functional configuration, circuit 100 may be a functional circuit within an IC, but in test configuration it appears as shown in FIG. 1. Scan architectures can be applied at various circuit levels. For example, the scan architecture of FIG. 1 may represent the testing of a complete IC, or it may represent the testing of an embedded intellectual property core sub-circuit within an IC, such as a DSP or CPU core sub-circuit.
The scan architecture includes an M-bit scan path 101, logic circuitry 102 to be tested, scan input 103, scan output 104, scan enable (SCANENA) 105, scan clock (SCANCK) 106, logic response outputs 107, and logic stimulus inputs 108. During scan testing, a tester or an embedded control circuit in the IC outputs SCANCK and SCANENA control signals to cause scan path 101 to repeat the operations of, (1) capturing data from logic 102 via response bus 107, and (2) scanning data through scan path 101 from scan input 103 to scan output 104. During the scan operation, the stimulus outputs 108 from scan path 101 ripple, which causes the inputs to logic 102 to actively change state. Rippling the inputs to logic 102 causes power to be consumed by the interconnect and gating capacitance of the circuits in logic 102.
In FIG. 2, a timing diagram example 200 depicts the signals used in the above described scan and capture operations. During scan operation, SCANENA is low from time 204 to 205 and M SCANCKs 201-202 are applied to shift data through the scan path 101. During capture operation, SCANENA is high and a SCANCK 203 is applied to capture response data into the scan path 101. Logical testing of logic 102 is achieved by inputting stimulus and capturing response. Delay testing of logic 102 is achieved by capturing the response data, via SCANCK 203, immediately following the last scan-in operation that occurs at SCANCK 202. For example, the last shift operation at SCANCK 202 moves or shifts all the stimulus inputs 108 to logic 102 one bit position, which causes the logic 102 to transition to output the final response 107 to scan path 101. The subsequent SCANCK 203 captures this final response transition into scan path 101. Thus the delay test is achieved by having the logic respond to a last stimulus transition during SCANCK 202 to output a last response pattern which is captured into scan path 101 during SCANCK 203. This form of scan path delay testing is well known.
In FIG. 3, a low power scan architecture 300 adaptation of the FIG. 1 scan path architecture is arranged according to the scan architectures described in the referenced patent application Ser. Nos. 09/803,588 and 09/803,608. As described in the referenced patent applications, the process of adapting scan architectures for low power operation is advantageously achieved without having to insert blocking circuitry in the stimulus paths, which increases overhead and adds delays, and without having to decrease the scan clock rate which increases test time. Furthermore, as described in the referenced applications, the process of adapting scan architectures for low power operation is advantageously achieved without having to modify the stimulus and response test patterns that are automatically produced by scan architecture synthesis tools.
Adapting the conventional scan path architecture 100 of FIG. 1 into the low power scan path architecture 300 of FIG. 3 involves reorganizing scan path 101 from being a single scan path containing all the scan cells (M), into a scan path having a desired number of separate scan paths. In FIG. 3, scan path 101 is shown after having been reorganized into three separate scan paths A, B, and C 301-303. For simplification, it is assumed that the number of scan cells (M) in the conventional scan path 101 of FIG. 1 is divisible by three such that each of the three separate scan paths A, B, and C of FIG. 3 contains an equal number of scan cells (M/3).
The serial input of each scan path A, B, and C is commonly connected to scan input 103. The serial output of scan path A is connected to the input of a 3-state buffer 304, the serial output of scan path B is connected to the input of a 3-state buffer 305, and the serial output of scan path C is connected to the input of a 3-state buffer 306. The outputs of the 3-state buffers 304-306 are commonly connected to scan output 104. Scan paths A, B, and C each output an equal number of parallel stimulus inputs (S) to logic 102, and each input an equal number of parallel response outputs (R) from logic 102. The number of stimulus output signals to logic 102 in from the scan architectures in FIGS. 1 and 3 is the same, and the number of response input signals from logic 102 in FIGS. 1 and 3 is the same.
Scan paths A-C and buffers 304-306 receive control input from an adaptor circuit which was described in detail in the referenced patent applications. These control inputs are labeled in FIG. 3 as; SCANENA, SCANCK-A, SCANCK-B, SCANCK-C, ENABUF-A, ENABUF-B, and ENABUF-C. Alternatively, these control inputs could be provided from IC pins/pads being driven by a tester, instead of from an adaptor circuit.
In FIG. 4, a timing diagram example 400 depicts the operation of the low power scan path of FIG. 3. As seen in the timing diagram, each scan operation, which begins at time 401 and ends at time 402, is broken up into a sequence of three sub-scan operations. The first sub-scan operation enables buffer 304 via ENABUF-A and shifts M/3 bits of data through Scan Path A 301 in response to the SCANCK-A's. The second sub-scan operation enables buffer 305 via ENABUF-B and shifts M/3 bits of data through Scan Path B 302 in response to the SCANCK-B's. The third sub-scan operation enables buffer 306 via ENABUF-C and shifts data through Scan Path C 303 in response to the SCANCK-C's. The effect of these sub-scan operations, as previously described in the referenced patent applications, is to reduce the number of simultaneously rippling stimulus inputs to logic 102 from M in FIG. 1 to M/3 in FIG. 3. Rippling only portions (M/3) of the overall stimulus input (M) to logic 102 advantageously reduces power consumption in logic 102 during scan operations.
From the signal timings in FIG. 4 it is seen that at the end of the sequence of sub-scan operations, at time 402, the SCANCKs-A, B, and C of Scan Paths A, B, and C are enabled at time 406 to capture response data into Scan Paths A, B, and C. During the sub-scan sequence, Scan Path A stops shifting data following SCANCK-A at time 403, Scan Path B stops shifting data following SCANCK-B at time 404, and Scan Path C stops shifting data following SCANCK-C at time 405. Since the response capture clock at time 406 occurs immediately after scan clock time 405, the logic portion of logic 102 stimulated by the last shift of Scan Path C does a delay test as described previously in regard to FIGS. 1 and 2. However, since the response capture clock time 406 does not occur immediately after the last shift time of Scan Path A and C, at times 403 and 404 respectively, it is not possible, with the timing shown in FIG. 4, to do delay testing of the logic portions of logic 102 that are stimulated by the last shift operations of Scan Paths A and B.